1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and data read method thereof which can stably output a data read from a memory cell array.
2. Description of Related Art
A conventional semiconductor memory device transmits data read from a memory cell array to common data I/O lines, and outputs the data transmitted to the common data I/O lines via a current-voltage converter, a differential amplifier (or latch), a data output buffer, and a data output driver.
In greater detail, the differential amplifier is arranged at an output stage of the current-voltage converter to amplify output data of the current-voltage converter and to transmit it to the data output buffer. Alternatively, a latch latches output data of the current-voltage converter and transmits it to the data output buffer.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device. The semiconductor memory device of FIG. 1 includes a memory cell array 10, current-voltage converters 20-1 to 20-n, differential amplifiers 22-1 to 22-n, data output buffers 24-1 to 24-n, and data output drivers 26-1 to 26-n.
In particular, in FIG. 1, IVC denotes the current-voltage converters, DA denotes the differential amplifiers, DOB denotes the data output buffers, and DOD denotes the data output drivers. LIO11/B to LIO1n/B, . . . , LIOm1/B to LIOmn/B denote local data I/O line pairs, and MIO1/B to MIOn/B denote main data I/O line pairs.
Functions of the components of FIG. 1 are described focusing on a read operation. Data stored in the memory cell array 10 is transferred to the local data I/O line pairs LIO11/B to LIO1n/B, . . . , LIOm1/B to LIOmn/B and to the main data I/O data line pairs MIO1/B to MIOn/B, in sequence. The current-voltage converters 20-1 to 20-n convert a current difference of the data pairs transferred to the main data I/O line pairs MIO1/B to MIOn/B, respectively, into a voltage difference to generate data X. The data output buffers 24-1 to 24-n buffer the data Z output from the differential amplifiers 22-1 to 22-n, respectively. The data output drivers 26-1 to 26-n drive the data output from the data output buffers 24-1 to 24-n to output data D1 to Dn, respectively.
FIGS. 2A to 2C are timing diagrams illustrating operation of the current-voltage converter and the differential amplifier. FIG. 2A shows the timing diagram during normal operation, FIG. 2B shows the timing diagram during a high-frequency operation, and FIG. 2C shows the timing diagram according to a process variation.
In FIGS. 2A to 2C, CLK denotes a clock signal, CMD denotes a command signal, and a hatched portion denotes an invalid data period.
Referring to FIG. 2A, data CSA1 to CSA4 are output from the current-voltage converters 20-1 to 20-n in sequence. When a signal Y is input so as to enable the differential amplifiers 22-1 to 22-n, the differential amplifiers 22-1 to 22-n sequentially receive the data CSAL to CSA4 and sequentially generate the data DO1 to DO4 in response to the signal Y. Period xe2x80x9ct1xe2x80x9d represents a time period from a time point that the clock signal CLK is generated when the read command is applied to a time point that the first data CSAL begins to be output through the current-voltage converters 20-1 to 20-n. Period xe2x80x9ct2xe2x80x9d represents a time period from a time point that the clock signal CLK is generated when the read command is applied to a time point that the signal Y is generated. A time period xe2x80x9ct3xe2x80x9d represents an enable period of the signal Y.
Referring to FIG. 2B, a cycle that the clock signal CLK is generated becomes faster, and the data CSA1 to CSA4 are sequentially output from the current-voltage converters 20-1 to 20-n in response to the clock signal CLK. The differential amplifiers 22-1 to 22-n receive the data CSA1 to CSA4 and generate data DO1 to DO4 in response to the signal Y. At this point, when the data CSA2 is input to the differential amplifiers 22-1 to 22-n during the enable period t3 of the signal Y, the differential amplifiers 22-1 to 22-n output not the data DO1 but the next data DO2. This is because when the data is transited during the enable period t3 of the differential amplifiers 22-1 to 22-n, the output data of the differential amplifiers 22-1 to 22-n is changed. Accordingly, since the data DO1 cannot be output in case of FIG. 2B, a data read error occurs. That is, in FIG. 2B, the data DO2 to DO4 are cut partially, but the data DO2 to DO4 are connected to be output by the data output buffers.
Referring to FIG. 2C, due to a process variation, the data CSA1 to CSA4 output from the current-voltage converters 20-1 to 20-n are delayed by a time period t4. Even though the data CSA1 to CSA4 are delayed by the time period t4, when the data CSA1 to CSA4 are input within the enable period t3 of the signal Y, the differential amplifiers 22-1 to 22-n can output the data DO1 to DO4 stably. In FIG. 2C, the data DO1 to DO4 are cut partially, but the data DO1 to DO4 are connected to be output by the data output buffers. Therefore, the data read error does not occur.
When a data read path of the semiconductor memory device is configured by the current-voltage converter and the differential amplifier, a data read error occurs during the high-frequency operation but the data read error resulting from the process variation does not occur.
FIG. 3 is a block diagram illustrating a configuration of a data read path of another conventional semiconductor memory device. The semiconductor memory device of FIG. 3 includes a memory cell array 10, current-voltage converters 20-1 to 20-n, latches 28-1 to 28-n, data output buffers 24-1 to 24-n, and data output drivers 26-1 to 26-n.
In FIG. 3, LA denotes the latch. Like references of FIGS. 1 and 3 denote like parts. The latch LA latches and outputs output data of the current-voltage converters 20-1 to 20-n in response to the signal Y. The remaining components of FIG. 3 except the latch LA can be understood with reference to the description of FIG. 1, and thus their description is omitted to avoid a redundancy.
FIGS. 4A to 4C are timing diagrams illustrating operation of the current-voltage converter and the latch. FIG. 4A shows the timing diagram during normal operation, FIG. 4B shows the timing diagram during a high-frequency operation, and FIG. 4C shows the timing diagram according to a process variation.
In FIGS. 4A to 4C, CLK denotes a clock signal, CMD denotes a command signal, and a hatched portion denotes an invalid data period.
Referring to FIG. 4A, data CSA1 to CSA4 are output from the current-voltage converters 20-1 to 20-n in sequence. The latches 28-1 to 28-n sequentially receive the data CSA1 to CSA4 and sequentially generate the data DO1 to DO4 in response to the signal Y. Period xe2x80x9ct1xe2x80x9d represents a time period from a time point that the clock signal CLK is generated when the read command is applied to a time point that the first data CSA1 begins to be output through the current-voltage converters 20-1 to 20-n. Period xe2x80x9ct2xe2x80x9d represents a time period from a time point that the clock signal CLK is generated when the read command is applied to a time point that the signal Y is generated. Period xe2x80x9ct3xe2x80x9d represents an enable period of the signal Y.
Referring to FIG. 4B, a generation cycle of the clock signal CLK becomes faster, and the data CSA1 to CSA4 are sequentially output from the current-voltage converters 20-1 to 20-n in response to the clock signal CLK. The latches 28-1 to 28-n receive and latch the data CSA1 to CSA4 and generate the data DO1 to DO4 at a rising edge of the signal Y.
The latches 28-1 to 28-n maintain the signals latched at a rising edge of the signal Y xe2x80x9cas isxe2x80x9d even though a state of the data output from the current-voltage converters 20-1 to 20-n is varied during the enable period t3 of the signal Y. Accordingly, the data read error does not occur.
Referring to FIG. 4C, due to a process variation, the data CSA1 to CSA4 output from the current-voltage converters 20-1 to 20-n are delayed by a time period t4. The latches 28-1 to 28-n latch the invalid data at a rising edge of the signal Y and thus cannot output the data DO1. The latches 28-1 to 28-n latch the data CSAL to CSA4 and output the data DO2 to DO4 in response to the signal Y. In this case, the data DO1 cannot be output, leading to a data read error.
As described above, when the latches 28-1 to 28-n are arranged at output stages of the current-voltage converters 20-1 to 20-n, the data can be output stably during the high-frequency operation, but when the process variation occurs, the invalid data is output.
When the conventional semiconductor memory device is configured to include the current-voltage converter and the differential amplifier in the data read path, the data read error occurs during high-frequency operation, whereas the data can be output stably when the process is varied. On the other hand, when the conventional semiconductor memory device is configured to include the current-voltage converter and the latch in the data read path, the data can be output stably during high-frequency operation, whereas the data read error occurs when the process is varied.
CAS latency is defined as the period of time in clock cycles between when a read command is applied to a semiconductor memory device and when valid data are applied at the outputs of the device, wherein the number of clock cycles is an integer. For example, a CAS latency of 2 means that valid data are output from the device two clock cycles after the read command is applied.
When the CAS latency is 2, the semiconductor memory device requires a frequency characteristic lower than when the CAS latency is 3. When the CAS latency is 3, the semiconductor memory device requires a time tAA, i.e., the data read speed not higher and a frequency characteristic higher than when the CAS latency is 2.
Accordingly, the data read error can be reduced by outputting the output data of the current-voltage converter through the latch in case of the CAS latency operation that is relatively high in need for a frequency characteristic during a read operation, and by outputting the output data of the current-voltage converter through the differential amplifier in case of the CAS latency operation that is relatively low in need for a frequency characteristic during a read operation.
It is an object of the present invention to provide a semiconductor memory device which can output data stably by differentiating data read paths in a read operation that have a high need for frequency performance characteristics from those in a read operation that is relatively low in need for a frequency performance characteristic during the read operation.
It is another object of the present invention to provide a data read method which can output data in a stable fashion.
The present invention is directed to a semiconductor memory device. The device includes a memory cell array and a differential amplifying and latching circuit for latching and outputting each of signal pairs output from the memory cell array in case of a first latency operation, and for amplifying a voltage difference of each of the signal pairs output from the memory cell array in case of a second latency operation.
The present invention further provides a semiconductor memory device which includes a memory cell array, a latch means for latching and outputting each of signal pairs output from the memory cell array in case of a first latency operation and a differential amplifying circuit for amplifying and outputting each of the signal pairs output from the memory cell array in case of a second latency operation.
The present invention further provides a semiconductor memory device that includes a memory cell array, a first amplifying circuit for amplifying and outputting signals output from the memory cell array in case of a first latency operation, and a second amplifying circuit for amplifying and outputting the signals output from the memory cell array in case of a second latency operation.
The present invention further provides a method of reading data in a semiconductor memory device. In accordance with the method, data is read from a memory cell array. In the case of a first latency operation, data output from the memory cell array is latched and output. In the case of a second latency operation, the data output from the memory cell array is amplified and output.